An Fpga Implementation of a Risc-V Based Soc System for Image Processing Applications

Gholizadehazari, ErfanAyhan, TubaOrs, Berna2021-08-242021-08-242021Gholizadehazari, E., Ayhan, T., & Ors, B. (9-11 June 2021). An FPGA Implementation of a RISC-V Based SoC System for Image Processing Applications. In 2021 29th Signal Processing and Communications Applications Conference (SIU) (pp. 1-4). https://doi.org/10.1109/SIU53274.2021.9477998https://hdl.handle.net/20.500.11779/1543https://doi.org/10.1109/SIU53274.2021.9477998The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.eninfo:eu-repo/semantics/closedAccessCamerasImage processingStreaming mediaRandom access memoryHardwareSoftwareLaplace equationsAn Fpga Implementation of a Risc-V Based Soc System for Image Processing ApplicationsConference Object10.1109/SIU53274.2021.94779982-s2.0-85111470201