Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11779/1750
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dc.contributor.authorKöseoğlu, İlayda-
dc.contributor.authorÖztürk, Elif-
dc.contributor.authorAyhan, Tuba-
dc.contributor.authorYalçın, Mustak Erhan-
dc.date.accessioned2022-03-14T11:44:32Z
dc.date.available2022-03-14T11:44:32Z
dc.date.issued2022-
dc.identifier.citationKoseoglu, I., Ozturk, E., Ayhan, T., & Yalcin, M. E. (21 January 2022). An FPGA Implementation of Givens Rotation Based Digital Architecture for Computing Eigenvalues of Asymmetric Matrix. In 2021 13th International Conference on Electrical and Electronics Engineering (ELECO) pp. 470-474. IEEE. https://doi.org//10.23919/ELECO54474.2021.9677749.en_US
dc.identifier.isbn9786050114379-
dc.identifier.urihttps://hdl.handle.net/20.500.11779/1750-
dc.identifier.urihttps://doi.org//10.23919/ELECO54474.2021.9677749-
dc.description.abstractThis paper proposes the digital circuit design that performs the eigenvalue calculation of asymmetric matrices with realvalued elements. Eigenvalues are computed iteratively through the QR algorithm. In the QR algorithm, the input matrix is factorized into orthogonal Q and upper triangular R matrix, then the RQ product is calculated to obtain an iterated matrix. For a time-efficient QR decomposition process, the Givens Rotation (GR) Principle is utilized to benefit from the parallelization feature. Parallelization is managed by the Systolic Array (SA) architecture that is created by placing Givens Generation (GG) and Row Updates (RU) blocks in a triangle array. In this paper, 4×4 input matrix is used to create a TSA architecture including n-1 diagonal (GG), and (n ∗ (n−1))/2 off-diagonal (RU) modules. In the results section, Givens Rotation is compared with the Gram Schmidt algorithm used in our previous study [1] in terms of error, and area usage.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectTime-frequency analysisen_US
dc.subjectDigital systemsen_US
dc.subjectComputer architectureen_US
dc.subjectEigenvalues and eigenfunctionsen_US
dc.subjectSystolic arraysen_US
dc.subjectMatrix decompositionen_US
dc.subjectIP networksen_US
dc.titleAn FPGA implementation of givens rotation based digital architecture for computing eigenvalues of asymmetric matrixen_US
dc.typeConference Objecten_US
dc.identifier.doi10.23919/ELECO54474.2021.9677749-
dc.identifier.scopus2-s2.0-85125248868en_US
dc.authoridTuba Ayhan / 0000-0002-1447-0770-
dc.description.PublishedMonthOcaken_US
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.identifier.endpage474en_US
dc.identifier.startpage470en_US
dc.departmentMühendislik Fakültesi, Elektrik Elektronik Mühendisliği Bölümüen_US
dc.relation.journal2021 13th International Conference on Electrical and Electronics Engineering (ELECO), 25-27 Nov. 2021en_US
dc.institutionauthorAyhan, Tuba-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.grantfulltextopen-
item.languageiso639-1en-
item.cerifentitytypePublications-
item.fulltextWith Fulltext-
item.openairetypeConference Object-
crisitem.author.dept02.05. Department of Electrical and Electronics Engineering-
Appears in Collections:Elektrik Elektronik Mühendisliği Bölümü koleksiyonu
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
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