Ayhan, Tuba

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Profile URL
https://hdl.handle.net/20.500.11779/2711
Name Variants
Ayhan T.
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Email Address
ayhant@mef.edu.tr
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02.05. Department of Electrical and Electronics Engineering
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Current Staff
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0000-0002-1447-0770
Scopus Author ID
36052413700
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WoS Researcher ID
AAF-6448-2021
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1728694850-academic-1604023676.avif (18.05 KB)

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JournalCount
2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)2
2021 13th International Conference on Electrical and Electronics Engineering (ELECO)1
2021 29th Signal Processing and Communications Applications Conference (SIU)1
2020 28th Signal Processing and Communications Applications Conference (SIU)1
21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design-SMACD -- JUL 07-10, 2025 -- Istanbul, TURKIYE1
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  • Thumbnail Image
    Conference Object
    Citation - Scopus: 1
    An Fpga Implementation of Givens Rotation Based Digital Architecture for Computing Eigenvalues of Asymmetric Matrix
    (IEEE, 2022) Köseoğlu, İlayda; Yalçın, Mustak Erhan; Öztürk, Elif; Ayhan, Tuba
    This paper proposes the digital circuit design that performs the eigenvalue calculation of asymmetric matrices with realvalued elements. Eigenvalues are computed iteratively through the QR algorithm. In the QR algorithm, the input matrix is factorized into orthogonal Q and upper triangular R matrix, then the RQ product is calculated to obtain an iterated matrix. For a time-efficient QR decomposition process, the Givens Rotation (GR) Principle is utilized to benefit from the parallelization feature. Parallelization is managed by the Systolic Array (SA) architecture that is created by placing Givens Generation (GG) and Row Updates (RU) blocks in a triangle array. In this paper, 4×4 input matrix is used to create a TSA architecture including n-1 diagonal (GG), and (n ∗ (n−1))/2 off-diagonal (RU) modules. In the results section, Givens Rotation is compared with the Gram Schmidt algorithm used in our previous study [1] in terms of error, and area usage.
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    Conference Object
    Live Demo: Design and Fpga Implementation of a Component Level Uav Simulator
    (IEEE, 2023) Aydın, Yusuf; Ayhan, Tuba; Akyavaş , İrfan
    In this work, we introduce a fast, component based simulation environment for UAVs. The simulator framework is proposed as combination of three sub-models: i. battery, ii. BLDC and propeller, iii. dynamic model. The model parameters are extracted for a particular UAV for testing the simulator. The simulator is implemented on an FPGA to increase simulation speed. The simulator calculates battery SOC, position, velocity and acceleration of the UAV with gravity, drag, propeller air inflow velocity. The simulator runs on the FPGA fabric of XilinxXCKU13P with simulation steps of 1 ms.
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    Master Thesis
    MQTT protocol data security with OTP blockchain-based identity and data verification
    (MEF Üniversitesi, 2023) Parlakay, Batuhan; Ayhan, Tuba
    Son yıllarda teknolojinin hızla gelişmesiyle birlikte, Nesnelerin İnterneti (IoT) adını verdiğimiz akıllı cihazlar ve sistemler hayatımızın her alanında kendine yer bulmaktadır. IoT, akıllı telefonlar, tabletler, PC'ler ve üzerinde sensör bulunan neredeyse her şeyi kapsayan geniş bir kavramdır. Bu kapsamda, IoT cihazları arasında verimli ve güvenli iletişim sağlamak amacıyla MQTT protokolü önemli bir role sahiptir. Bu tezde, MQTT protokolünün güvenlik zafiyetlerini tespit etmek ve bu zafiyetlere karşı etkili önlemler geliştirmek hedeflenmektedir. Tez kapsamında, Raspberry Pi ve bilgisayar arasında MQTT server client mimarisi oluşturulmuştur. MQTT Broker ve yayıncı/abone istemcileri için Python programları geliştirilmiş, sistem üzerinde çeşitli güvenlik açıklarını tespiti sağlanırken Shodan API'sinden ve Wireshark'dan yararlanılmıştır. Bu süreçte, paket ve konu düzeyindeki güvenlik sorunları deneysel olarak incelenmiştir. Akıllı sözleşmeler, dijital imzalar, OTP kullanarak 1883 numaralı portunda bir yapı geliştirilmiştir. Bu, yayıncı ve abone için kimlik doğrulama ve şifreleme sağlayarak yalnızca yetkili kullanıcıların MQTT brokerine bağlanmasına olanak tanır. Kimlik doğrulama, mesaj reddetme, veri bütünlüğü ve seçici gizlilik gibi ek güvenlik önlemleri sunulmaktadır. MQTT brokerına erişim, veri yayınlama veya okuma isteyen bir kullanıcının sadece gerekli yetkiye sahip olması yetmez, aynı zamanda benzersiz OTP (Tek Seferlik Şifre) bilgilerine dayalı olarak dijital imzalı bir mesajı onaylaması da gereklidir. Bu imza Elips Kavisli Dijital İmza Algoritması'na dayanır. Erişim izinlerine sahip kullanıcılar, dijital imzayı genel anahtar ve OTP bilgilerini kullanarak doğrulayabilirler. Dijital imzalar, asimetrik şifreleme tekniklerini kullanarak, iletilen her bir MQTT mesajının bütünlüğünü ve kökenini doğrular. Bu, iletilen verinin değiştirilmediğini ve belirli bir cihaz veya kullanıcıdan geldiğini garantiler. SSL/TLS, bağlantı bazında çalışır ve tüm bağlantıyı şifreler. Geniş ölçekteki sistemlerde, SSL/TLS sertifikalarının yönetimi ve sürekli şifreleme/şifre çözme işlemleri, özellikle düşük kapasiteli IoT cihazlarında ek işlem yükü oluşturabilir. Akıllı sözleşmeler ve dijital imzaların kullanımı, geniş ölçekteki çok sayıda yayınlayıcı ve abone içeren sistemlerde, SSL/TLS'ye göre daha ölçeklenebilir bir çözüm sunabilir. Tez çalışması sonucunda, geliştirilen güvenlik önlemleri sayesinde Broker'ın saldırılara karşı bağışık olduğu tespit edilmiştir. Bu tez, MQTT protokolündeki güvenlik tutarsızlıklarının ve alınabilecek önlemlerin özlü bir incelemesini sunarak, alanındaki çalışmalara katkı sağlamayı hedeflemektedir. Bu sayede, IoT sistemlerinde veri iletişiminin daha güvenli ve etkin bir şekilde gerçekleştirilmesine yardımcı olunacaktır.
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    Conference Object
    Citation - Scopus: 6
    System-On Based Driver Drowsiness Detection and Warning System
    (IEEE, 2022) Yazici, Berkay; Ayhan, Tuba; Özdemir, Arda
    The aim of this project is to detect the drowsiness level of the driver in the vehicle, to warn the driver and to prevent possible accidents. Percentage Eye Closure (PERCLOS) and Convolutional Neural Network (CNN) are used to detect drowsiness. The system is implemented on Xilinx PYNQ-Z2 development board. The system is tested under real world conditions in real time. A high accuracy rate of 92% and a fast working system with 0.8 s is achieved. A speaker is activated to warn the driver when drowsiness is detected. Moreover, the drowsiness information is sent to the cloud by using a Wi-Fi module.
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    Citation - WoS: 3
    Citation - Scopus: 10
    An Fpga Implementation of a Risc-V Based Soc System for Image Processing Applications
    (IEEE, 2021) Gholizadehazari, Erfan; Ayhan, Tuba; Ors, Berna
    The Laplacian filter is one of the fundamental applications in image processing. In our work, the Laplacian filter has been applied to an image, and both hardware and software implementation of the filter has been studied. Our system consists of an OV7670 Camera module, Nexys 4 DDR FPGA board and VGA monitor to display the processed video stream. Mentioned process has forwarding tasks: camera module captures raw RGB data and writes to RAM, Laplacian filter IP processes raw image and the results written back to memory. VGA modules show output images to monitor. The Laplacian filter part considered in hardware and software implementation is compared in terms of time and area.
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    Citation - Scopus: 1
    Design and Fpga Implementation of Uav Simulator for Fast Prototyping
    (IEEE, 2023) Aydın, Yusuf; Ayhan, Tuba; Akyavaş , İrfan
    As production and advances in motor and battery cell technology progress, unmanned aerial vehicles (UAVs) are gaining more and more acceptance and popularity. Unfortunately, the design and prototyping of UAVs is an expensive and long process. This paper proposes a fast, component based simulation environment for UAVs so that they can be roughly tested without a damage risk. Moreover, the combined effect of individual component choices can be observed with the simulator to reduce design time. The simulator is flexible in the sense that detailed aerodynamic effects and selected components models can be included. In this work, the simulator is proposed, model parameters are extracted for a particular UAV for testing the simulator and it is implemented on an field programmable gate array (FPGA) to increase simulation speed. The simulator calculates battery state of charge (SOC), position, velocity and acceleration of the UAV with gravity, drag, propeller air inflow velocity. The simulator runs on the FPGA fabric of AMD-XCKU13P with simulation steps of 1 ms.
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    Citation - Scopus: 1
    Solving Xor In Spike Neural Network (SNN) With Component-off-the-shelf
    (Institute of Electrical and Electronics Engineers Inc., 2024) Cikikci, S.V.; Orek, E.; Ozgen, A.K.; Yavuz, A.; Ayhan, Tuğba
    This paper addresses the solution of the XOR problem with Spiking Neural Networks (SNN) in order to improve energy efficiency and computational performance as Moore's Law approaches its limits. SNN is capable of solving nonlinear problems while saving energy by mimicking the working principles of biological neurons. For this purpose, a SNN consisting of 12 neurons was implemented on a breadboard using the Leaky Integrate and Fire (LIF) model. In the input layer of the network, 50 Hz and 100 Hz signals are processed with frequency sensitive filters. With the help of bandpass and low-pass filters, additive and inverting operational amplifiers, the XOR problem is successfully solved. © 2024 IEEE.
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    A Practical PCB-Based Framework for Spiking Neural Networks with a Half-Adder Example
    (IEEE, 2025) Cikikci, Sevde Vuslat; Orek, Eren; Aysoy, Ayhan; Ozgen, Ali Kagan; Yavuz, Arda; Ayhan, Tuba
    This paper addresses the half-adder problem using Spiking Neural Networks (SNNs). In a previous study, the XOR operation was successfully realized on a breadboard and in this study it is integrated into the half-adder structure. The system uses input signals at frequencies of 50 Hz and 100 Hz and the neurons are generated by the Leaky Integrate and Fire (LIF) model. Unlike other neuron models, the LIF model is less complex. In addition, it was preferred because of its biological meaningfulness compared to the Integrate and Fire model. The network, consisting of 18 neurons in total, shows that basic arithmetic operations can be performed with SNN. Overall, this study demonstrates that basic logic operations can be implemented in neural networks, thus providing new perspectives for digital calculation. The successful solution of the Half Adder problem using SNNs not only proves the calculation capabilities of SNNs, but also opens new perspectives for the development of more complex logical circuits using these biologically inspired neural circuits.
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    Zamanla Değişen Iır Alçak Geçiren Filtre ile Dinamik Tartım Yöntemi
    (2022) Gülbaş, Mustafa Can; Ayhan, Tuba; Yalçın, Müştak Erhan
    Sanayide üretimden sevkiyat aşamasına kadar birçok alanda kullanılan otomatik ağırlık kontrol sistemi, üç adet konveyör bant, en az iki adet fotosel, yük hücresi, işlemci, kullanıcı için kontrol ekranı ve reddedici/yönlendirici kollarından oluşmaktadır. Ağırlık ölçerken, yük hücresi tarafından alınan ölçüm sinyalinin filtrelenmesi aşamasında literatürde kaskat yapıda zamanla değişen alçak geçiren filtrenin önemli bir yeri olduğu gözlemlenmiş ancak sonuca ulaşma konusunda oldukça fazla filtre adedinin mevcut olduğu gözlemlenmiştir. Sonuçlara ulaşma aşamasının hızlandırılması amacıyla bu çalışmada zamanla değişen alçak geçiren filtre ile farklı bir yaklaşım denenmiştir. Sonuca daha hızlı ulaşabilmek için kaskat bağlı alçak geçiren filtre adedi önem arz etmektedir. Filtre adım adım uygulanarak oluşan salınımlardan ürünün ağırlığına minimum filtre adedi ile ulaşmak hedeflenmiştir. Matlab'ta yapılan deneyler sonucunda çok yüksek hızlarda bu işlemle yönetmelikte belirtilen hata limitleri içerisinde sonuçların elde edilemediği görülmüş olup hata limitleri içerisinde elde edilen maksimum hız belirtilmiştir. Sonuç olarak filtre adedi azaltılıp, sönümleme hızlandırılarak oluşan salınımlardan ağırlık verisine yönetmelikte verilen hata sınırları içerisinde ulaşılmıştır.
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    Impact of Hardware Sources on Feature Selection for Online Signature Verification
    (IEEE, 2020) Ayhan, Tuba; Orak, Remzi
    This work analyzes time series features gathered from a touchpad which is a part of online signature verification system. A DTW processing unit is implemented on FPGA to be used in time series analysis. To support different feature groups, this unit can be reconfigured without altering the memory structure. By using this reconfigurable unit, features are evaluated according to the area cost that they introduce. Moreover, a method to predict the value of features for classification is introduced. This way, minimum requirements to implement an online signature verification system on FPGA are partially obtained.